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order number: 290580, revision: 020 18 aug 2005 intel ? advanced boot block flash memory (b3) 28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet product features the intel ? advanced boot block flash memory (b3) device, manufactured on the intel 0.13 m and 0.18 m technologies, is a feature-rich solution at a low system cost. the b3 device in x16 is available in 48-lead tsop and 48-ball csp packages. the x8 option of this product family is available only in 40-lead tsop and 48-ball bga* packages. for additional information about this product family, see the intel website: http://www.intel.com/design/flash . flexible smartvoltage technology ? 2.7 v ? 3.6 v read/program/erase ?12 v v pp fast production programming 1.65 v ? .5 v or 2.7 v ? 3.6 v i/o option ? reduces overall system power high performance ? 2.7 v ? 3.6 v: 70 ns max access time optimized block sizes ? eight 8-kb blocks for data, top or bottom locations ? up to 127 x 64-kb blocks for code block locking ?v cc -level control through write protect wp# low power consumption ? 9 ma typical read current absolute hardware-protection ?v pp = gnd option ?v cc lockout voltage extended temperature operation ? ?40 c to +85 c automated program and block erase ? status registers intel ? flash data integrator software ?flash memory manager ?system interrupt manager ?supports parameter storage, streaming data (for example, voice) extended cycling capability ?minimum 100,000 block erase cycles automatic power savings feature ?typical i ccs after bus inactivity standard surface mount packaging ?48-ball csp packages ?40-lead and 48-lead tsop packages density and footprint upgradeable for common package ?8-, 16-, 32-, and 64-mbit densities etox? viii (0.13 m ) flash technology ?16-mbit and 32-mbit densities etox? vii (0.18 m ) flash technology ?16-, 32-, and 64-mbit densities etox ? vi (0.25 m ) flash technology ?8-, 16-, and 32-mbit densities bo not use the x8 option for new designs notice: this specification is subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 2 order number: 290580, revision: 020 information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuc lear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel ? advanced boot block flash memory (b3) may contain design defects or errors known as errata which may cause the product to devi ate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800 548-4725 or by visiting intel's website at http://www.intel.com. intel, the intel logo, and etox are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 3 contents 1.0 introduction ............................................................................................................................... 7 1.1 nomenclature ................................................................................................................ ....... 7 1.2 conventions................................................................................................................. .........8 2.0 functional overview ..............................................................................................................8 3.0 functional overview ..............................................................................................................9 3.1 architecture diagram ........................................................................................................ ..10 3.2 memory maps and block organization............................................................................... 11 3.2.1 parameter blocks ..................................................................................................11 3.2.2 main blocks ...........................................................................................................11 3.2.3 4-mbit, 8-mbit, 16-mbit, 32-mbit, and 64-mbit word-wide memory maps ............. 11 3.2.4 4-mbit, 8-mbit, and 16-mbit byte-wide memory maps...........................................20 4.0 package information ............................................................................................................24 4.1 mbga* and very thin profile fine pitch ball grid array (vf bga) package ....................24 4.2 tsop package ................................................................................................................ ... 25 4.3 easy bga package ............................................................................................................ 26 5.0 pinout and signal descriptions .......................................................................................27 5.1 signal pinouts .............................................................................................................. .......27 5.1.1 40-lead and 48-lead tsop packages ................................................................. 27 5.2 signal descriptions ......................................................................................................... ....30 6.0 maximum ratings and operating conditions ...........................................................32 6.1 absolute maximum ratings ................................................................................................32 6.2 operating conditions ........................................................................................................ ..33 7.0 electrical specifications .....................................................................................................34 7.1 dc current characteristics .................................................................................................3 4 7.2 dc voltage characteristics.................................................................................................3 6 8.0 ac characteristics ................................................................................................................37 8.1 ac read characteristics ....................................................................................................3 7 8.2 ac write characteristics.................................................................................................... .41 8.3 erase and program timing .................................................................................................45 8.4 ac i/o test conditions ...................................................................................................... .46 8.5 device capacitance.......................................................................................................... ..46 9.0 power and reset specifications .....................................................................................47 9.1 power-up/down characteristics.........................................................................................47 9.1.1 rp# connected to system reset .......................................................................... 47 9.1.2 v cc , v pp, and rp# transitions..............................................................................47 9.2 reset specifications ........................................................................................................ ... 48 9.3 power supply decoupling...................................................................................................49
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 4 order number: 290580, revision: 020 9.4 power consumption ........................................................................................................... 49 9.4.1 active power.......................................................................................................... 49 9.4.2 automatic power savings (aps) ...........................................................................49 9.4.3 standby power ...................................................................................................... 49 9.4.4 deep power-down mode....................................................................................... 50 10.0 operations overview ........................................................................................................... 50 10.1 bus operations............................................................................................................. ......51 10.1.1 read ..................................................................................................................... .51 10.1.2 output disable....................................................................................................... 52 10.1.3 standby.................................................................................................................. 52 10.1.4 deep power-down / reset .................................................................................... 52 10.1.5 write .................................................................................................................... .. 53 11.0 operating modes ...................................................................................................................53 11.1 read array................................................................................................................. ......... 54 11.2 read identifier ............................................................................................................ ........ 56 11.3 read status register....................................................................................................... ... 56 11.3.1 clearing the status register..................................................................................57 11.4 program mode............................................................................................................... ..... 57 11.4.1 suspending and resuming programming ............................................................. 58 11.5 erase mode ................................................................................................................. ....... 58 11.5.1 suspending and resuming erase ......................................................................... 59 12.0 block locking ......................................................................................................................... 62 12.1 wp# = v il for block locking............................................................................................... 62 12.2 wp# = v ih for block unlocking........................................................................................... 62 13.0 v pp program and erase voltages ................................................................................... 63 13.1 v pp = v il for complete protection...................................................................................... 63 14.0 additional information ........................................................................................................ 63 appendix a write state machine current/next states .................................................64 appendix b program and erase flowcharts ....................................................................66 appendix c ordering information .........................................................................................70
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 5 revision history revision number description -001 original version -002 section 3.4, v pp program and erase voltages , added updated figure 9: automated block erase flowchart updated figure 10: erase suspend/resume flowchart (added program to table) updated figure 16: ac waveform: program and erase operations (updated notes) i ppr maximum specification change from 25 a to 50 a program and erase suspend latency specification change updated appendix a: ordering information (included 8 m and 4 m information) updated figure, appendix d: architecture block diagram (block info. in words not bytes) minor wording changes -003 combined byte-wide specification (previously 290605) with this document improved speed specification to 80 ns (3.0 v) and 90 ns (2.7 v) improved 1.8 v i/o option to minimum 1.65 v (section 3.4) improved several dc characteristics (section 4.4) improved several ac characteristics (sections 4.5 and 4.6) combined 2.7 v and 1.8 v dc characteristics (section 4.4) added 5 v v pp read specification (section 3.4) removed 120 ns and 150 ns speed offerings moved ordering information from appendix to section 6.0; updated information moved additional information from appendix to section 7.0 updated figure appendix b, access time vs. capacitive load updated figure appendix c, architecture block diagram moved program and erase flowcharts to appendix e updated program flowchart updated program suspend/resume flowchart minor text edits throughout -004 added 32-mbit density added 98h as a reserved command (table 4) a 1 ?a 20 = 0 when in read identifier mode (section 3.2.2) status register clarification for sr3 (table 7) v cc and v ccq absolute maximum specification = 3.7 v (section 4.1) combined i ppw and i ccw into one specification (section 4.4) combined i ppe and i cce into one specification (section 4.4) max parameter block erase time (t whqv2 /t ehqv2 ) reduced to 4 sec (section 4.7) max main block erase time (t whqv3 /t ehqv3 ) reduced to 5 sec (section 4.7) erase suspend time @ 12 v (t whrh2 /t ehrh2 ) changed to 5 s typical and 20 s maximum (section 4.7) ordering information updated (section 6.0) write state machine current/next states table updated (appendix a) program suspend/resume flowchart updated (appendix f) erase suspend/resume flowchart updated (appendix f) text clarifications throughout -005 bga package diagrams corrected (figures 3 and 4) i ppd test conditions corrected (section 4.4) 32-mbit ordering information corrected (section 6) bga package top side mark information added (section 6) -006 v ih and v il specification change (section 4.4) i ccs test conditions clarification (section 4.4) added command sequence error note (table 7) data sheet renamed from smart 3 advanced boot block 4-mbit, 8-mbit, 16-mbit flash memory family. added device id information for 4-mbit x8 device removed 32-mbit x8 to reflect product offerings minor text changes
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 6 order number: 290580, revision: 020 -007 corrected rp# pin description in table 2, 3 volt advanced boot block pin descriptions corrected typographical error fixed in ordering information -008 4-mbit packaging and addressing information corrected throughout document -009 corrected 4-mbit memory addressing tables in appendices d and e -010 max i ccd changed to 25 a v cc max on 32 m (28f320b3) changed to 3.3 v -011 added 64-mbit density and faster speed offerings removed access time vs. capacitance load curve -012 changed references of 32mbit 80ns devices to 70ns devices to reflect the faster product offering. changed vccmax=3.3v reference to indicate the affected product is the 0.25 m 32mbit device. minor text edits throughout document. -013 added new pin-1 indicator information on 40 and 48lead tsop packages. minor text edits throughout document. -014 added specifications for 0.13 micron product offerings throughout document -015 minor text edits throughout document. -016 adjusted ordering information. adjusted specifications for 0.13 micron product offerings. revised and corrected dc characteristics table. adjusted package diagram information. minor text edits throughout document. -017 updated ordering information. adjusted specifications for 0.13 micron product offerings. updated ac/dc characteristics table. added tsop and bga* package diagram information. minor text edits throughout document. -018 updated the layout of the datasheet. -019 added line items to table 34 ?ordering information: valid combinations? on page 70 . -020 removed all x8 products from ordering information, page 70 revision number description
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 7 1.0 introduction this datasheet describes the specifications for the intel ? advanced boot block flash memory (b3) device (hereafter referred to as the b3 flash memory device). the b3 flash memory device is optimized for portable, low-power, systems. this family of products features 1.65 v to 2.5 v or 2.7 v to 3.6 v i/os, and a low v cc /v pp operating range of 2.7 v to 3.6 v for read, program, and erase operations. the b3 device is also capable of fast programming at 12 v. throughout this document: 2.7 v refers to the full voltage range 2.7 v to 3.6 v (except where noted otherwise). v pp = 12 v refers to 12 v 5%. 1.1 nomenclature table 1. nomenclature term definition 0x hexadecimal prefix 0b binary prefix byte 8 bits word 16 bits kw or kword 1024 words mword 1,048,576 words kb 1024 bits kb 1024 bytes mb 1,048,576 bits mb 1,048,576 bytes aps automatic power savings csp chip scale package cui command user interface otp one time programmable pr protection register prd protection register data plr protection lock register rfu reserved for future use sr status register srd status register data wsm write state machine
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 8 order number: 290580, revision: 020 1.2 conventions 2.0 functional overview the b3 flash memory device features the following: enhanced blocking for easy segmentation of code and data or additional design flexibility. program suspend to read command. v ccq input of 1.65 v to 2.5 v or 2.7 v to 3.6 v on all i/os. see figure 1 through figure 4 for pinout diagrams and v ccq location. maximum program and erase time specification for improved data storage. table 2. conventions convention description pin or signal used interchangeably to refer to the external signal connections on the package. note: for a chip scale package (csp), the term ball is used in place of pin . group membership brackets square brackets designate group membership or define a group of signals with similar function (for example, a[21:1], sr[4:1]) set when referring to registers, the term set means the bit is a logical 1. clear: when referring to registers, the term clear means the bit is a logical 0. block a group of bits (or words) that erase simultaneously using one block erase instruction. main block a block that contains 32 kwords. parameter block a block that contains 4 kwords. table 3. b3 device feature summary (sheet 1 of 2) feature 28f008b3, 28f016b3 28f800b3, 28f160b3, 28f320b3 (3) , 28f640b3 reference v cc read voltage 2.7 v? 3.6 v section 6.2 , section 7.2 v ccq i/o voltage 1.65 v?2.5 v or 2.7 v? 3.6 v section 4.2, 4.4 v pp program/erase voltage 2.7 v? 3.6 v or 11.4 v? 12.6 v section 4.2, 4.4 bus width 8 bit 16 bit table 27 speed 70 ns, 80 ns, 90 ns, 100 ns, 110 ns section 8.1 memory arrangement 1024 kbit x 8 (8 mbit), 2048 kbit x 8 (16 mbit) 512 kbit x 16 (8 mbit), 1024 kbit x 16 (16 mbit), 2048 kbit x 16 (32 mbit), 4096 kbit x 16 (64 mbit) section 3.2
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 9 3.0 functional overview intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: v cc for read operation v ccq for output swing v pp for program and erase operation. all b3 flash memory devices provide program/erase capability at 2.7 v or 12 v (for fast production programming), and read with v cc at 2.7 v. because many designs read from the flash memory a large percentage of the time, 2.7 v v cc operation can provide substantial power savings. the b3 flash memory device family is available in either x8 or x16 packages in the following densities (see appendix c, ?ordering information,? for availability): 8-mbit (8, 388, 608-bit) flash memory organized as 512 kwords of 16 bits each or 1024 kbytes of 8-bits each. 16-mbit (16, 777, 216-bit) flash memory organized as 1024 kwords of 16 bits each or 2048 kbytes of 8-bits each. 32-mbit (33, 554, 432-bit) flash memory organized as 2048 kwords of 16 bits each. 64-mbit (67, 108, 864-bit) flash memory organized as 4096 kwords of 16 bits each. the parameter blocks are located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map, to accommodate different microprocessor protocols for kernel code location. the upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. locking and unlocking is controlled by write protect wp# (see section 12.0, ?block locking? on page 62 for details). blocking (top or bottom) eight 8-kbyte parameter blocks and fifteen 64-kbyte blocks (8 mbit) or thirty-one 64-kbyte main blocks (16 mbit) sixty-three 64-kbyte main blocks (32 mbit) one hundred twenty-seven 64-kbyte main blocks (64 mbit) section 3.2, ?memory maps and block organization? on page 11 locking wp# locks/unlocks parameter blocks all other blocks protected using v pp section 12.0 table 32 operating temperature extended: ?40 c to +85 c section 6.2 , section 7.2 program/erase cycling 100,000 cycles section 6.2 , section 7.2 packages 40-lead tsop (1) , 48-ball bga* csp (2) 48-lead tsop, 48-ball bga csp (2) , 48-ball vf bga figure 8 , figure 9 notes: 1. 32-mbit and 64-mbit densities not available in 40-lead tsop. 2. 8-mbit densities not available in bga* csp. 3. v cc max is 3.3 v on 0.25 m 32-mbit devices. table 3. b3 device feature summary (sheet 2 of 2) feature 28f008b3, 28f016b3 28f800b3, 28f160b3, 28f320b3 (3) , 28f640b3 reference
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 10 order number: 290580, revision: 020 the command user interface (cui) is the interface between the microprocessor or microcontroller and the internal operation of the flash memory. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations (including verification), which unburdens the microprocessor or microcontroller. to indicate the status of the wsm, the status register signifies block erase or word program completion and status. the b3 flash memory device also provides automatic power savings (aps), which minimizes system current drain and allows for very low power designs. this mode is entered following the completion of a read cycle (approximately 300 ns later). the rp# pin provides additional protection against unwanted command writes that might occur during system reset and power-up/down sequences due to invalid system bus conditions (see ?power and reset specifications? on page 47 ). section 10.0, ?operations overview? on page 50 explains the different modes of operation. section 7.0, ?electrical specifications? on page 34 and section 8.0, ?ac characteristics? on page 37 provide complete current and voltage specifications. section 8.1, ?ac read characteristics? on page 37 provides read, program, and erase performance specifications. 3.1 architecture diagram figure 1. b3 architecture block diagram output multiplexer 4-kword parameter block 32-kword main block 32-kword main block 4-kword parameter block y-gating/sensing write state machine program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder power reduction control input buffer output buffer gnd v cc v pp ce# we# oe# rp# command user interface input buffer a 0 -a 19 dq 0 -dq 15 v ccq wp#
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 11 3.2 memory maps and block organization the b3 flash memory device uses an asymmetrically blocked architecture, enabling system integration of code and data within a single flash memory device. each block can be erased independently of other blocks up to 100,000 times. for the address locations of each block, see the following memory maps: table 4 ?16-mbit and 32-mbit word-wide memory addressing map? on page 11 table 5 ?4-mbit and 8-mbit word-wide memory addressing map? on page 14 table 6 ?16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map? on page 15 table 7 ?8-mbit and 16-mbit byte-wide memory addressing map? on page 20 table 8 ?4-mbit byte wide memory addressing map? on page 23 3.2.1 parameter blocks the b3 flash memory device architecture includes parameter blocks to facilitate storing frequently updated small parameters (such as data traditionally stored in an eeprom). the word-rewrite functionality of eeproms can be emulated using software techniques. each flash memory device contains eight parameter blocks of 8 kbytes/4 kwords (8192 bytes/4,096 words) each. 3.2.2 main blocks after the parameter blocks, the remainder of the flash memory array is divided into equal-size main blocks (65,536 bytes/32,768 words) for data or code storage. the 8-mbit flash memory device contains 15 main blocks. the 16-mbit flash memory device contains 31 main blocks. the 32-mbit memory device contains 63 main blocks. the 64-mbit memory device contains 127 main blocks. 3.2.3 4-mbit, 8-mbit, 16-mbit, 32-mbit, and 64-mbit word-wide memory maps table 4. 16-mbit and 32-mbit word-wide memory addressing map (sheet 1 of 4) 16-mbit and 32-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit size (kw) 8 mbit 16 mbit 32 mbit 4 ff000-fffff 1ff000-1fffff 32 1f8000-1fffff 4 fe000-fefff 1fe000-1fefff 32 1f0000-1f7fff 4 fd000-fdfff 1fd000-1fdfff 32 1e8000- 1effff 4 fc000-fcfff 1fc000-1fcfff 32 1e0000- 1e7fff
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 12 order number: 290580, revision: 020 4 fb000-fbfff 1fb000-1fbfff 32 1d8000- 1dffff 4 fa000-fafff 1fa000-1fafff 32 1d0000- 1d7fff 4 f9000-f9fff 1f9000-1f9fff 32 1c8000- 1cffff 4 f8000-f8fff 1f8000-1f8fff 32 1c0000- 1c7fff 32 f0000-f7fff 1f0000-1f7fff 32 1b8000- 1bffff 32 e8000-effff 1e8000-1effff 32 1b0000- 1b7fff 32 e0000-e7fff 1e0000-1e7fff 32 1a8000- 1affff 32 d8000-dffff 1d8000-1dffff 32 1a0000- 1a7fff 32 d0000-d7fff 1d0000-1d7fff 32 198000-19ffff 32 c8000-cffff 1c8000-1cffff 32 190000-197fff 32 c0000-c7fff 1c0000-1c7fff 32 188000-18ffff 32 b8000-bffff 1b8000-1bffff 32 180000-187fff 32 b0000-b7fff 1b0000-1b7fff 32 178000-17ffff 32 a8000-affff 1a8000-1affff 32 170000-177fff 32 a0000-a7fff 1a0000-1a7fff 32 168000-16ffff 32 98000-9ffff 198000-19ffff 32 160000-167fff 32 90000-97fff 190000-197fff 32 158000-15ffff 32 88000-8ffff 188000-18ffff 32 150000-157fff 32 80000-87fff 180000-187fff 32 148000-14ffff 32 78000-7ffff 178000-17ffff 32 140000-147fff 32 70000-77fff 170000-177fff 32 138000-13ffff 32 68000-6ffff 168000-16ffff 32 130000-137fff 32 60000-67fff 160000-167fff 32 128000-12ffff 32 58000-5ffff 158000-15ffff 32 120000-127fff 32 50000-57fff 150000-157fff 32 118000-11ffff 32 48000-4ffff 148000-14ffff 32 110000-117fff 32 40000-47fff 140000-147fff 32 108000-10ffff 32 38000-3ffff 138000-13ffff 32 100000-107fff 32 30000-37fff 130000-137fff 32 f8000-fffff 0f8000-0fffff 32 28000-2ffff 128000-12ffff 32 f0000-f7fff 0f0000-0f7fff table 4. 16-mbit and 32-mbit word-wide memory addressing map (sheet 2 of 4) 16-mbit and 32-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit size (kw) 8 mbit 16 mbit 32 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 13 32 20000-27fff 120000-127fff 32 e8000-effff 0e8000- 0effff 32 18000-1ffff 118000-11ffff 32 e0000-e7fff 0e0000- 0e7fff 32 10000-17fff 110000-117fff 32 d8000-dffff 0d8000- 0dffff 32 08000-0ffff 108000-10ffff 32 d0000-d7fff 0d0000- 0d7fff 32 00000-07fff 100000-107fff 32 c8000-cffff 0c8000- 0cffff this column continues on next page this column continues on next page 32 0f8000-0fffff 32 c0000-c7fff 0c0000- 0c7fff 32 0f0000-0f7fff 32 b8000-bffff 0b8000- 0bffff 32 0e8000-0effff 32 b0000-b7fff 0b0000- 0b7fff 32 0e0000-0e7fff 32 a8000-affff 0a8000- 0affff 32 0d8000-0dffff 32 a0000-a7fff 0a0000- 0a7fff 32 0d0000-0d7fff 32 98000-9ffff 098000-09ffff 32 0c8000-0cffff 32 90000-97fff 090000-097fff 32 0c0000-0c7fff 32 88000-8ffff 088000-08ffff 32 0b8000-0bffff 32 80000-87fff 080000-087fff 32 0b0000-0b7fff 32 78000-7ffff 78000-7ffff 32 0a8000-0affff 32 70000-77fff 70000-77fff 32 0a0000-0a7fff 32 68000-6ffff 68000-6ffff 32 098000-09ffff 32 60000-67fff 60000-67fff 32 090000-097fff 32 58000-5ffff 58000-5ffff 32 088000-08ffff 32 50000-57fff 50000-57fff 32 080000-087fff 32 48000-4ffff 48000-4ffff 32 078000-07ffff 32 40000-47fff 40000-47fff 32 070000-077fff 32 38000-3ffff 38000-3ffff 32 068000-06ffff 32 30000-37fff 30000-37fff 32 060000-067fff 32 28000-2ffff 28000-2ffff 32 058000-05ffff 32 20000-27fff 20000-27fff 32 050000-057fff 32 18000-1ffff 18000-1ffff 32 048000-04ffff 32 10000-17fff 10000-17fff 32 040000-047fff 32 08000-0ffff 08000-0ffff table 4. 16-mbit and 32-mbit word-wide memory addressing map (sheet 3 of 4) 16-mbit and 32-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit size (kw) 8 mbit 16 mbit 32 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 14 order number: 290580, revision: 020 038000-03ffff 4 07000-07fff 07000-07fff 030000-037fff 4 06000-06fff 06000-06fff 028000-02ffff 4 05000-05fff 05000-05fff 020000-027fff 4 04000-04fff 04000-04fff 018000-01ffff 4 03000-03fff 03000-03fff 010000-017fff 4 02000-02fff 02000-02fff 008000-00ffff 4 01000-01fff 01000-01fff 000000-007fff 4 00000-00fff 00000-00fff table 5. 4-mbit and 8-mbit word-wide memory addressing map (sheet 1 of 2) 4-mbit and 8-mbit word-wide memory addressing top boot bottom boot size (kw) 4 mbit size (kw) 4 mbit 8 mbit 3f000-3ffff 7f000-7ffff 32 78000-7ffff 3e000-3efff 7e000-7efff 32 70000-77fff 3d000-3dfff 7d000-7dfff 32 68000-6ffff 3c000-3cfff 7c000-7cfff 32 60000-67fff 3b000-3bfff 7b000-7bfff 32 58000-5ffff 3a000-3afff 7a000-7afff 32 50000-57fff 39000-39fff 79000-79fff 32 48000-4ffff 38000-38fff 78000-78fff 32 40000-47fff 4 30000-37fff 70000-77fff 32 38000-3ffff 38000-3ffff 4 28000-2ffff 68000-6ffff 32 30000-37fff 30000-37fff 4 20000-27fff 60000-67fff 32 28000-2ffff 28000-2ffff 4 18000-1ffff 58000-5ffff 32 20000-27fff 20000-27fff 4 10000-17fff 50000-57fff 32 18000-1ffff 18000-1ffff 4 08000-0ffff 48000-4ffff 32 10000-17fff 10000-17fff 4 00000-07fff 40000-47fff 32 08000-0ffff 08000-0ffff 4 38000-3ffff 4 07000-07fff 07000-07fff 32 30000-37fff 4 06000-06fff 06000-06fff 32 28000-2ffff 4 05000-05fff 05000-05fff 32 20000-27fff 4 04000-04fff 04000-04fff 32 18000-1ffff 4 03000-03fff 03000-03fff le 4. 16-mbit and 32-mbit word-wide memory addressing map (sheet 4 of 4) 16-mbit and 32-mbit word-wide memory addressing top boot bottom boot ize w) 16 mbit 32 mbit size (kw) 8 mbit 16 mbit 32 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 15 32 10000-17fff 4 02000-02fff 02000-02fff 32 08000-0ffff 4 01000-01fff 01000-01fff 32 00000-07fff 4 00000-00fff 00000-00fff table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 1 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit 4 ff000-fffff 1ff000- 1fffff 3ff000-3fffff 32 3f8000- 3fffff 4 fe000-fefff 1fe000- 1fefff 3fe000-3fefff 32 3f0000- 3f7fff 4 fd000-fdfff 1fd000- 1fdfff 3fd000-3fdfff 32 3e8000- 3effff 4 fc000-fcfff 1fc000- 1fcfff 3fc000-3fcfff 32 3e0000- 3e7fff 4 fb000-fbfff 1fb000- 1fbfff 3fb000-3fbfff 32 3d8000- 3dffff 4 fa000-fafff 1fa000- 1fafff 3fa000-3fafff 32 3d0000- 3d7fff 4 f9000-f9fff 1f9000- 1f9fff 3f9000-3f9fff 32 3c8000- 3cffff 4 f8000-f8fff 1f8000- 1f8fff 3f8000-3f8fff 32 3c0000- 3c7fff 32 f0000-f7fff 1f0000- 1f7fff 3f0000-3f7fff 32 3b8000- 3bffff 32 e8000-effff 1e8000- 1effff 3e8000-3effff 32 3b0000- 3b7fff 32 e0000-e7fff 1e0000- 1e7fff 3e0000-3e7fff 32 3a8000- 3affff 32 d8000-dffff 1d8000- 1dffff 3d8000-3dffff 32 3a0000- 3a7fff 32 d0000-d7fff 1d0000- 1d7fff 3d0000-3d7fff 32 398000-39ffff 32 c8000-cffff 1c8000- 1cffff 3c8000-3cffff 32 390000-397fff 32 c0000-c7fff 1c0000- 1c7fff 3c0000-3c7fff 32 388000-38ffff 32 b8000-bffff 1b8000- 1bffff 3b8000-3bffff 32 380000-387fff table 5. 4-mbit and 8-mbit word-wide memory addressing map (sheet 2 of 2) 4-mbit and 8-mbit word-wide memory addressing top boot bottom boot size (kw) 4 mbit size (kw) 4 mbit 8 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 16 order number: 290580, revision: 020 32 b0000-b7fff 1b0000- 1b7fff 3b0000-3b7fff 32 378000-37ffff 32 a8000-affff 1a8000- 1affff 3a8000-3affff 32 370000-377fff 32 a0000-a7fff 1a0000- 1a7fff 3a0000-3a7fff 32 368000-36ffff 32 98000-9ffff 198000- 19ffff 398000-39ffff 32 360000-367fff 32 90000-97fff 190000- 197fff 390000-397fff 32 358000-35ffff 32 88000-8ffff 188000- 18ffff 388000-38ffff 32 350000-357fff 32 80000-87fff 180000- 187fff 380000-387fff 32 348000-34ffff 32 78000-7ffff 178000- 17ffff 378000-37ffff 32 340000-347fff 32 70000-77fff 170000- 177fff 370000-377fff 32 338000-33ffff 32 68000-6ffff 168000- 16ffff 368000-36ffff 32 330000-337fff 32 60000-67fff 160000- 167fff 360000-367fff 32 328000-32ffff 32 58000-5ffff 158000- 15ffff 358000-35ffff 32 320000-327fff 32 50000-57fff 150000- 157fff 350000-357fff 32 318000-31ffff 32 48000-4ffff 148000- 14ffff 348000-34ffff 32 310000-317fff 32 40000-47fff 140000- 147fff 340000-347fff 32 308000-30ffff 32 38000-3ffff 138000- 13ffff 338000-33ffff 32 300000-307fff 32 30000-37fff 130000- 137fff 330000-337fff 32 2f8000- 2fffff 32 28000-2ffff 128000- 12ffff 328000-32ffff 32 2f0000- 2f7fff 32 20000-27fff 120000- 127fff 320000-327fff 32 2e8000- 2effff 32 18000-1ffff 118000-11ffff 318000-31ffff 32 2e0000- 2e7fff 32 10000-17fff 110000-117fff 310000-317fff 32 2d8000- 2dffff table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 2 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 17 32 08000-0ffff 108000- 10ffff 308000-30ffff 32 2d0000- 2d7fff 32 00000-07fff 100000- 107fff 300000-307fff 32 2c8000- 2cffff 32 0f8000- 0fffff 2f8000-2fffff 32 2c0000- 2c7fff 32 0f0000- 0f7fff 2f0000-2f7fff 32 2b8000- 2bffff 32 0e8000- 0effff 2e8000-2effff 32 2b0000- 2b7fff 32 0e0000- 0e7fff 2e0000-2e7fff 32 2a8000- 2affff 32 0d8000- 0dffff 2d8000-2dffff 32 2a0000- 2a7fff 32 0d0000- 0d7fff 2d0000-2d7fff 32 298000-29ffff 32 0c8000- 0cffff 2c8000-2cffff 32 290000-297fff 32 0c0000- 0c7fff 2c0000-2c7fff 32 288000-28ffff 32 0b8000- 0bffff 2b8000-2bffff 32 280000-287fff 32 0b0000- 0b7fff 2b0000-2b7fff 32 278000-27ffff 32 0a8000- 0affff 2a8000-2affff 32 270000-277fff 32 0a0000- 0a7fff 2a0000-2a7fff 32 268000-26ffff 32 098000- 09ffff 298000-29ffff 32 260000-267fff 32 090000- 097fff 290000-297fff 32 258000-25ffff 32 088000- 08ffff 288000-28ffff 32 250000-257fff 32 080000- 087fff 280000-287fff 32 248000-24ffff 32 078000- 07ffff 278000-27ffff 32 240000-247fff 32 070000- 077fff 270000-277fff 32 238000-23ffff 32 068000- 06ffff 268000-26ffff 32 230000-237fff table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 3 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 18 order number: 290580, revision: 020 32 060000- 067fff 260000-267fff 32 228000-22ffff 32 058000- 05ffff 258000-25ffff 32 220000-227fff 32 050000- 057fff 250000-257fff 32 218000-21ffff 32 048000- 04ffff 248000-24ffff 32 210000-217fff 32 040000- 047fff 240000-247fff 32 208000-20ffff 32 038000- 03ffff 238000-23ffff 32 200000-207fff 32 030000- 037fff 230000-237fff 32 1f8000- 1fffff 1f8000- 1fffff 32 028000- 02ffff 228000-22ffff 32 1f0000- 1f7fff 1f0000- 1f7fff 32 020000- 027fff 220000-227fff 32 1e8000- 1effff 1e8000- 1effff 32 018000- 01ffff 218000-21ffff 32 1e0000- 1e7fff 1e0000- 1e7fff 32 010000- 017fff 210000-217fff 32 1d8000- 1dffff 1d8000- 1dffff 32 008000- 00ffff 208000-21ffff 32 1d0000- 1d7fff 1d0000- 1d7fff 32 000000- 007fff 200000-207fff 32 1c8000- 1cffff 1c8000- 1cffff 32 1f8000-1fffff 32 1c0000- 1c7fff 1c0000- 1c7fff 32 1f0000-1f7fff 32 1b8000- 1bffff 1b8000- 1bffff 32 1e8000-1effff 32 1b0000- 1b7fff 1b0000- 1b7fff 32 1e0000-1e7fff 32 1a8000- 1affff 1a8000- 1affff 32 1d8000-1dffff 32 1a0000- 1a7fff 1a0000- 1a7fff 32 1d0000-1d7fff 32 198000-19ffff 198000-19ffff 32 1c8000-1cffff 32 190000-197fff 190000-197fff 32 1c0000-1c7fff 32 188000-18ffff 188000-18ffff 32 1b8000-1bffff 32 180000-187fff 180000-187fff 32 1b0000-1b7fff 32 178000-17ffff 178000-17ffff 32 1a8000-1affff 32 170000-177fff 170000-177fff table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 4 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 19 32 1a0000-1a7fff 32 168000-16ffff 168000-16ffff 32 198000-19ffff 32 160000-167fff 160000-167fff 32 190000-197fff 32 158000-15ffff 158000-15ffff 32 188000-18ffff 32 150000-157fff 150000-157fff 32 180000-187fff 32 148000-14ffff 148000-14ffff 32 178000-17ffff 32 140000-147fff 140000-147fff 32 170000-177fff 32 138000-13ffff 138000-13ffff 32 168000-16ffff 32 130000-137fff 130000-137fff 32 160000-167fff 32 128000-12ffff 128000-12ffff 32 158000-15ffff 32 120000-127fff 120000-127fff 32 150000-157fff 32 118000-11ffff 118000-11ffff 32 148000-14ffff 32 110000-117fff 110000-117fff 32 140000-147fff 32 108000-10ffff 108000-10ffff 32 138000-13ffff 32 100000-107fff 100000-107fff 32 130000-137fff 32 f8000-fffff f8000-fffff f8000-fffff 32 128000-12ffff 32 f0000-f7fff f0000-f7fff f0000-f7fff 32 120000-127fff 32 e8000-effff e8000-effff e8000-effff 32 118000-11ffff 32 e0000-e7fff e0000-e7fff e0000-e7fff 32 110000-117fff 32 d8000-dffff d8000-dffff d8000-dffff 32 108000-10ffff 32 d0000-d7fff d0000-d7fff d0000-d7fff 32 100000-107fff 32 c8000-cffff c8000-cffff c8000-cffff 32 0f8000-0fffff 32 c0000-c7fff c0000-c7fff c0000-c7fff 32 0f0000-0f7fff 32 b8000-bffff b8000-bffff b8000-bffff 32 0e8000-0effff 32 b0000-b7fff b0000-b7fff b0000-b7fff 32 0e0000-0e7fff 32 a8000-affff a8000-affff a8000-affff 32 0d8000-0dffff 32 a0000-a7fff a0000-a7fff a0000-a7fff 32 0d0000-0d7fff 32 98000-9ffff 98000-9ffff 98000-9ffff 32 0c8000-0cffff 32 90000-97fff 90000-97fff 90000-97fff 32 0c0000-0c7fff 32 88000-8ffff 88000-8ffff 88000-8ffff 32 0b8000-0bffff 32 80000-87fff 80000-87fff 80000-87fff 32 0b0000-0b7fff 32 78000-7ffff 78000-7ffff 78000-7ffff 32 0a8000-0affff 32 70000-77fff 70000-77fff 70000-77fff 32 0a0000-0a7fff 32 68000-6ffff 68000-6ffff 68000-6ffff 32 098000-09ffff 32 60000-67fff 60000-67fff 60000-67fff 32 090000-097fff 32 58000-5ffff 58000-5ffff 58000-5ffff table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 5 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 20 order number: 290580, revision: 020 3.2.4 4-mbit, 8-mbit, and 16-mbit byte-wide memory maps 32 088000-08ffff 32 50000-57fff 50000-57fff 50000-57fff 32 080000-087fff 32 48000-4ffff 48000-4ffff 48000-4ffff 32 078000-07ffff 32 40000-47fff 40000-47fff 40000-47fff 32 070000-077fff 32 38000-3ffff 38000-3ffff 38000-3ffff 32 068000-06ffff 32 30000-37fff 30000-37fff 30000-37fff 32 060000-067fff 32 28000-2ffff 28000-2ffff 28000-2ffff 32 058000-05ffff 32 20000-27fff 20000-27fff 20000-27fff 32 050000-057fff 32 18000-1ffff 18000-1ffff 18000-1ffff 32 048000-04ffff 32 10000-17fff 10000-17fff 10000-17fff 32 040000-047fff 32 08000-0ffff 08000-0ffff 08000-0ffff 32 038000-03ffff 4 07000-07fff 07000-07fff 07000-07fff 32 030000-037fff 4 06000-06fff 06000-06fff 06000-06fff 32 028000-02ffff 4 05000-05fff 05000-05fff 05000-05fff 32 020000-027fff 4 04000-04fff 04000-04fff 04000-04fff 32 018000-01ffff 4 03000-03fff 03000-03fff 03000-03fff 32 010000-017fff 4 02000-02fff 02000-02fff 02000-02fff 32 008000-00ffff 4 01000-01fff 01000-01fff 01000-01fff 32 000000-007fff 4 00000-00fff 00000-00fff 00000-00fff table 7. 8-mbit and 16-mbit byte-wide memory addressing map (sheet 1 of 3) 8-mbit and 16-mbit byte-wide byte-wide memory addressing top boot bottom boot size (kb) 8 mbit 16 mbit size (kb) 8 mbit 16 mbit 8 fe000-fffff 1fe000-1fffff 64 8 fc000-fdfff 1fc000-1fdfff 64 8 fa000-fbfff 1fa000-1fbfff 64 8 f8000-f9fff 1f8000-1f9fff 64 8 f6000-f7fff 1f6000-1f7fff 64 8 f4000-f5fff 1f4000-1f5fff 64 8 f2000-f3fff 1f2000-1f3fff 64 8 f0000-f1fff 1f0000-1f1fff 64 table 6. 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing map (sheet 6 of 6) 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16 mbit 32 mbit 64 mbit size (kw) 16 mbit 32 mbit 64 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 21 64 e0000-effff 1e0000-1effff 64 64 d0000-dffff 1d0000-1dffff 64 64 c0000-cffff 1c0000-1cffff 64 64 b0000-bffff 1b0000-1bffff 64 64 a0000-affff 1a0000-1affff 64 64 90000-9ffff 190000-19ffff 64 64 80000-8ffff 180000-18ffff 64 64 70000-7ffff 170000-17ffff 64 64 60000-6ffff 160000-16ffff 64 64 50000-5ffff 150000-15ffff 64 64 40000-4ffff 140000-14ffff 64 64 30000-3ffff 130000-13ffff 64 64 20000-2ffff 120000-12ffff 64 64 10000-1ffff 110000-11ffff 64 64 00000-0ffff 100000-10ffff 64 64 0f0000-0fffff 64 64 0e0000-0effff 64 64 0d0000-0dffff 64 64 0c0000-0cffff 64 64 0b0000-0bffff 64 64 0a0000-0affff 64 64 090000-09ffff 64 64 080000-08ffff 64 64 070000-07ffff 64 64 060000-06ffff 64 1f0000-1fffff 64 050000-05ffff 64 1e0000-1effff 64 040000-04ffff 64 1d0000-1dffff 64 030000-03ffff 64 1c0000-1cffff 64 020000-02ffff 64 1b0000-1bffff 64 010000-01ffff 64 1a0000-1affff 64 000000-00ffff 64 190000-19ffff 64 64 180000-18ffff 64 64 170000-17ffff 64 64 160000-16ffff 64 64 150000-15ffff table 7. 8-mbit and 16-mbit byte-wide memory addressing map (sheet 2 of 3) 8-mbit and 16-mbit byte-wide byte-wide memory addressing top boot bottom boot size (kb) 8 mbit 16 mbit size (kb) 8 mbit 16 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 22 order number: 290580, revision: 020 64 64 140000-14ffff 64 64 130000-13ffff 64 64 120000-12ffff 64 64 110000-11ffff 64 64 100000-10ffff 64 64 f0000-fffff 0f0000-0fffff 64 64 e0000-effff 0e0000-0effff 64 64 d0000-dffff 0d0000-0dffff 64 64 c0000-cffff 0c0000-0cffff 64 64 b0000-bffff 0b0000-0bffff 64 64 a0000-affff 0a0000-0affff 64 64 90000-9ffff 090000-09ffff 64 64 80000-8ffff 080000-08ffff 64 64 70000-7ffff 070000-07ffff 64 64 60000-6ffff 060000-06ffff 64 64 50000-5ffff 050000-05ffff 64 64 40000-4ffff 040000-04ffff 64 64 30000-3ffff 030000-03ffff 64 64 20000-2ffff 020000-02ffff 64 64 10000-1ffff 010000-01ffff 64 8 0e000-0ffff 00e000-00ffff 64 8 0c000-0dfff 00c000-00dfff 64 8 0a000-0bfff 00a000-00bfff 64 8 08000-09fff 008000-009fff 64 8 06000-07fff 006000-007fff 64 8 04000-05fff 004000-005fff 64 8 02000-03fff 002000-003fff 64 8 00000-01fff 000000-001fff table 7. 8-mbit and 16-mbit byte-wide memory addressing map (sheet 3 of 3) 8-mbit and 16-mbit byte-wide byte-wide memory addressing top boot bottom boot size (kb) 8 mbit 16 mbit size (kb) 8 mbit 16 mbit
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 23 table 8. 4-mbit byte wide memory addressing map 4-mbit byte-wide memory addressing top boot bottom boot size (kb) 4 mbit size (kb) 4 mbit 8 7e000-7ffff 64 70000-7ffff 8 7c000-7dfff 64 60000-6ffff 8 7a000-7bfff 64 50000-5ffff 8 78000-79fff 64 40000-4ffff 8 76000-77fff 64 30000-3ffff 8 74000-75fff 64 20000-2ffff 8 72000-73fff 64 10000-1ffff 8 70000-71fff 8 0e000-0ffff 64 60000-6ffff 8 0c000-0dfff 64 50000-5ffff 8 0a000-0bfff 64 40000-4ffff 8 08000-09fff 64 30000-3ffff 8 06000-07fff 64 20000-2ffff 8 04000-05fff 64 10000-1ffff 8 02000-03fff 64 00000-0ffff 8 00000-01fff
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 24 order number: 290580, revision: 020 4.0 package information 4.1 bga* and very thin profile fine pitch ball grid array (vf bga) package figure 2. bga* and vf bga package drawing bottom view -bump side up e b s1 ball a1 corner top view - bump side down ball a1 corner e d side view a a2 a 1 seating y a b c d e f s2 plan 1 2 3 4 5 6 7 8 a b c d e f 123 4 5678 note: drawing not to scale millimeters inches dimensions symbol min nom max min nom max package height a 1.000 0.0394 ball height a1 0.150 0.0059 package body thicknes s a2 0.665 0.0262 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length 8m (.25) d 7.810 7.910 8.010 package body length 16m (.25/.18/.13) 32m (.25/.18/.13) d 7.186 7.286 7.386 0.2829 0.2868 0.2908 package body length 64m (.18) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width 8m (.25) e 6.400 6.500 6.600 0.2520 0.2559 0.2598 package body width 16m (.25/.18/.13) 32m (.18/.13) e 6.864 6.964 7.064 0.2702 0.2742 0.2781 package body width 32m (.25) e 10.750 10.850 10.860 0.4232 0.4272 0.4276 package body width 64m (.18) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch e 0.750 0.0295 ball (lead) count 8m, 16m n 46 46 ball (lead) count 32m n 47 47 ball (lead) count 64m n 48 48 seating plane coplanarity y 0.100 0.0039 corner to ball a1 dis tance along d 8m (.25) s1 1.230 1.330 1.430 0.0484 0.0524 0.0563 corner to ball a1 dis tance along d 16m (.25/.18/.13) 32m (.18/.13) s1 0.918 1.018 1.118 0.0361 0.0401 0.0440 corner to ball a1 dis tance along d 64m (.18) s1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 dis tance along e 8m (.25) s2 1.275 1.375 1.475 0.0502 0.0541 0.0581 corner to ball a1 dis tance along e 16m (.25/.18/.13) 32m (.18/.13) s2 1.507 1.607 1.707 0.0593 0.0633 0.0672 corner to ball a1 dis tance along e 32m (.25) s2 3.450 3.550 3.650 0.1358 0.1398 0.1437 corner to ball a1 dis tance along e 64m (.18) s2 2.525 2.625 2.725 0.0994 0.1033 0.1073
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 25 4.2 tsop package notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 is in the upper left corner of the package, in reference to the product mark. figure 3. tsop package drawing dimensions a5568-02 a 0 l det ail a y d c z pin 1 e d 1 b detail b see det ail a e se e d e ta il b a 1 a 2 sea tin g pla ne see notes 1, 2, 3 and 4 family: thin small out -line package symbol millimeters inches min nom max notes min nom max notes package height a 1.200 0.047 standoff a1 0.050 0.002 package body thickness a2 0.950 1.000 1.050 0.037 0.039 0.041 lead width b 0.150 0.200 0.300 0.006 0.008 0.012 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 plastic body length d1 18.200 18.400 18.600 0.717 0.724 0.732 package body width e 11.800 12.000 12.200 0.465 0.472 0.480 lead pitch e 0.500 0.0197 terminal dimension d 19.800 20.000 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 lead count n 48 48 lead tip angle ? 0 3 5 0 3 5 seating plane coplanarity y 0.100 0.004 lead to package offset z 0.150 0.250 0.350 0.006 0.010 0.014
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 26 order number: 290580, revision: 020 4.3 easy bga package figure 4. easy bga package drawing millimeters inches symbol min nom max notes min nom max package height a 1.200 0.0472 ball height a 1 0.250 0.0098 package body thickness a 2 0.780 0.0307 ball (lead) w idth b 0.330 0.430 0.530 0.0130 0.0169 0.0209 package body width d 9.900 10.000 10.100 1 0.3898 0.3937 0.3976 package body length e 12.900 13.000 13.100 1 0.5079 0.5118 0.5157 pitch [e] 1.000 0.0394 ball (lead) count n 64 64 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along d s 1 1.400 1.500 1.600 1 0.0551 0.0591 0.0630 corner to ball a1 distance along e s 2 2.900 3.000 3.100 1 0.1142 0.1181 0.1220 dimensions table note: (1) package dimensions are for reference only. these dimensions are estimates based on die size, and are subject to change. e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 8 7654321 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner side view
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 27 5.0 pinout and signal descriptions this section explains the package pinout and signal descriptions. 5.1 signal pinouts the b3 flash memory device is available in the following packages: 40-lead tsop (x8, figure 5 ). 48-lead tsop (x16, figure 6 ). 48-ball bga (x8 in figure 8 and x16 in figure 9 ). 48-ball vf bga (x16, figure 9 ). 5.1.1 40-lead and 48-lead tsop packages notes: 1. 40-lead tsop available for 8-mbit and 16-mbit densities only. 2. lower densities have nc on the upper address pins. for example, an 8-mbit device has nc on pin 38. figure 5. 40-lead tsop package for x8 configurations a 17 gnd a 20 a 19 a 10 dq 7 dq 6 dq 5 dq 4 v ccq v cc nc dq 3 dq 2 dq 1 dq 0 oe# gnd ce# a 0 a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we# rp# v pp wp# a 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 16 m 8 m advanced boot block 40-lead tsop 10 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 4 m
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 28 order number: 290580, revision: 020 note: the topside marking on 8-mb, 16-mb, and 32-mb intel ? advanced boot block 40l and 48l tsop products changed to a white ink triangle as a pin-1 indicator. products without the white triangle continue to use a dimple as a pin-1 indicator. no other changes were made in package size, materials, functionality, customer handling, or manufacturability. the product continues to meet stringent intel quality requirements. table 9 lists the ordering codes of the affected products. see also table 34 ?ordering information: valid combinations? on page 70 . figure 6. 48-lead tsop package for x16 configurations figure 7. new mark for pin-1 indicator: 40-lead 8/16 mb tsop and 48-lead 8/16/32 mb tsop advanced boot block 48-lead tsop 12 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 16 v ccq gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 21 a 20 we# rp# v pp wp# a 19 a 18 a 17 a 7 a 6 a 5 21 22 23 24 oe# gnd ce# a 0 28 27 26 25 a 4 a 3 a 2 a 1 32 m 16 m 64 m n ew mark:
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 29 notes: 1. a19 and a20 indicate the upgrade address connections. lower density devices do not have the upper address solder balls. do not route is not done in this area. a 20 is the upgrade address for the 16-mbit device. table 9. b3 flash memory device ordering information ordering information valid combinations 40-lead tsop 48-lead tsop ext. temp. 64 mbit te28f640b3tc70 te28f640b3bc70 ext. temp. 32 mbit te28f320b3td70 te28f320b3bd70 te28f320b3tc70 te28f320b3bc70 te28f320b3tc90 te28f320b3bc90 te28f320b3ta100 te28f320b3ba100 te28f320b3ta110 te28f320b3ba110 ext. temp. 16 mbit te28f160b3tc70 te28f160b3bc70 te28f160b3tc80 te28f160b3bc80 te28f016b3ta90 te28f016b3ba90 te28f160b3ta90 te28f160b3ba90 te28f016b3ta110 te28f016b3ba110 te28f160b3ta110 te28f160b3ba110 ext. temp. 8 mbit te28f008b3ta90 te28f008b3ba90 te28f800b3ta90 te28f800b3ba90 te28f008b3ta110 te28f008b3ba110 te28f800b3ta110 te28f800b3ba110 figure 8. x8 48-ball bga* chip size package (top view, ball down) a14 a15 a16 a17 v ccq a12 a10 a13 nc a11 a8 we# a9 d5 d6 v pp rp# nc wp# a19 d2 d3 a20 a18 a6 nc nc a7 a5 a3 ce# d0 a4 a2 a1 a0 gnd gnd d7 nc d4 v cc nc d1 oe# a b c d e f 13 25 47 68 16m 8m nc
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 30 order number: 290580, revision: 020 notes: 1. a19, a20, and a21 indicate the upgrade address connections. lower density devices do not have the upper address solder balls. do not route in this area. ? a 19 is the upgrade address for the 16-mbit device. ? a 20 is the upgrade address for the 32-mbit device. ? a 21 is the upgrade address for the 64-mbit device. 2. table 10 ?b3 flash memory device signal descriptions? on page 31 details the usage of each device pin. 5.2 signal descriptions table 10 describes the active signals. figure 9. x16 48-ball vf bga and bga* chip size package (top view, ball down) a b c d e f 13 25 47 68 a13 a14 a15 a16 v ccq a11 a10 a12 d14 d15 a8 we# a9 d5 d6 v pp rp# a21 d11 d12 wp# a18 a20 d2 d3 a19 a17 a6 d8 d9 a7 a5 a3 ce# d0 a4 a2 a1 a0 vss vss d7 d13 d4 v cc d10 d1 oe# 16m 32m 64m
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 31 table 10. b3 flash memory device signal descriptions (sheet 1 of 2) symbol type description a 0 ?a 21 input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. 28f008b3: a[0-19], 28f016b3: a[0-20], 28f800b3: a[0-18], 28f160b3: a[0-19], 28f320b3: a[0-20], 28f640b3: a[0-21] dq 0 ?dq 7 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched. outputs array, identifier and status register data. the data pins float to tristate when the chip is deselected or the outputs are disabled. dq 8 ?dq 15 input/ output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched. outputs array and identifier data. the data pins float to tristate when the chip is de-selected. not included on x8 products. ce# input chip enable: activates the internal control logic, input buffers, decoders, and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. oe# input output enable: enables the flash memory device outputs through the data buffers during a read operation. oe# is active low. we# input write enable: controls writes to the command register and memory array. we# is active low. addresses and data are latched on the rising edge of the second we# pulse. rp# input reset/deep power-down: uses two voltage levels (v il , v ih ) to control reset/deep power- down mode. when rp# is at logic low, the flash memory device is in reset/deep power-down mode , which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when rp# is at logic high, the flash memory device is in standard operation . when rp# transitions from logic-low to logic-high, the flash memory device defaults to the read array mode. wp# input write protect: locks and unlocks the two lockable parameter blocks. when wp# is at logic low, the lockable blocks are locked , preventing program and erase operations to those blocks. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [erase] are set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. see section 12.0, ?block locking? on page 62 for details on write protection. v ccq input output v cc : enables all outputs to be driven to 1.8 v to 2.5 v while the v cc is at 2.7 v to 3.3 v. if the v cc is regulated to 2.7 v to 2.85 v, v ccq can be driven at 1.65 v to 2.5 v to achieve lowest power operation (see section 7.2, ?dc voltage characteristics? on page 36 ) . this input can be tied directly to v cc (2.7 v to 3.6 v). v cc power device power supply: 2.7 v to 3.6 v
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 32 order number: 290580, revision: 020 6.0 maximum ratings and operating conditions 6.1 absolute maximum ratings warning: stressing the flash memory device beyond the absolute maximum ratings in table 11 can cause permanent damage. these ratings are stress ratings only. v pp power program/erase power supply: supplies power for program and erase operations. v pp can be the same as v cc (2.7 v to 3.6 v) for single supply voltage operation. for fast programming at manufacturing, 11.4 v to 12.6 v can be supplied to v pp . this pin cannot be left floating. 11.4 v to 12.6 v can be applied to v pp only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp can be connected to 12 v for a total of 80 hours maximum (see section 13.0, ?v pp program and erase voltages? on page 63 for details). v pp < v pplk protects memory contents against inadvertent or unintended program and erase commands. gnd ? ground: for all internal circuitry. all ground inputs must be connected. nc ? no connect: pin can be driven or left floating. notice: specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 11. absolute maximum ratings parameter maximum rating notes extended operating temperature during read ?40 c to +85 c during block erase and program ?40 c to +85 c temperature under bias ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any pin (except v cc and v pp ) with respect to gnd ?0.5 v to +3.7 v 1 v pp voltage (for block erase and program) with respect to gnd ?0.5 v to +13.5 v 1,2,3 v cc and v ccq supply voltage with respect to gnd ?0.2 v to +3.6 v output short circuit current 100 ma 4 notes: 1. minimum dc voltage is ?0.5 v on input/output pins. during transitions, this level might undershoot to ?2.0 v for periods <20 ns. maximum dc voltage on input/output pins is v cc +0.5 v which, during transitions, might overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp might overshoot to +14.0 v for periods <20 ns. 3. v pp program voltage is typically 1.65 v to 3.6 v. connection to a 11.4 v to 12.6 v supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp can be connected to 12 v for a total of 80 hours maximum. 4. output shorted for no more than one second. no more than one output shorted at a time. table 10. b3 flash memory device signal descriptions (sheet 2 of 2) symbol type description
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 33 6.2 operating conditions do not operate the flash memory device beyond the operating conditions in table 12 . extended exposure beyond the operating conditions can affect device reliability. table 12. temperature and voltage operating conditions symbol parameter min max units notes t a operating temperature ?40 +85 c v cc1 v cc supply voltage 2.7 3.6 volts 1, 2 v cc2 3.0 3.6 1, 2 v ccq1 i/o supply voltage 2.7 3.6 volts 1 v ccq2 1.65 2.5 v ccq3 1.8 2.5 v pp1 supply voltage 1.65 3.6 volts 1 v pp2 11.4 12.6 volts 1, 3 cycling block erase cycling 100,000 cycles 3 notes: 1. v cc and v ccq must share the same supply when they are in the v cc1 range. 2. v cc max = 3.3 v for 0.25 m 32-mbit devices. 3. v pp = 11.4 v?12.6 v can be applied during a program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp can be connected to 12 v for a total of 80 hours maximum.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 34 order number: 290580, revision: 020 7.0 electrical specifications 7.1 dc current characteristics table 13. dc current characteristics (sheet 1 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max i li input load current 1,2 1 1 1a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1,2 10 10 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current for 0.13 and 0.18 micron product 1 7 15 20 50 150 250 a v cc = v cc max ce# = rp# = v ccq or during program/ erase suspend wp# = v ccq or gnd v cc standby current for 0.25 micron product 1 10 25 20 50 150 250 a i ccd v cc power-down current for 0.13 and 0.18 micron product 1,2 7 15 7 20 7 20 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd rp# = gnd 0.2 v v cc power-down current for 0.25 product 1,2 7 25 7 25 7 25 a i ccr v cc read current for 0.13 and 0.18 micron product 1,2,3 9 18 8 15 9 15 ma v cc = v cc max v ccq = v ccq max oe# = v ih , ce# =v il f = 5 mhz, i out =0 ma inputs = v il or v ih v cc read current for 0.25 micron product 1,2,3 10 18 8 15 9 15 ma i ppd v pp deep power-down current 1 0.2 5 0.2 5 0.2 5 a rp# = gnd 0.2 v v pp v cc i ccw v cc program current 1,4 18 55 18 55 18 55 ma v pp =v pp1, program in progress 82210301030ma v pp = v pp2 (12v) program in progress i cce v cc erase current 1,4 16 45 21 45 21 45 ma v pp = v pp1, erase in progress 81516451645ma v pp = v pp2 (12v) , erase in progress i cces / i ccws v cc erase suspend current for 0.13 and 0.18 micron product 1,4,5 7 15 50 200 50 200 a ce# = v ih, erase suspend in progress v cc erase suspend current for 0.25 micron product 10 25 50 200 50 200 a i ppr v pp read current 1,4 2 15 2 15 2 15 a v pp v cc 50 200 50 200 50 200 a v pp > v cc
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 35 i ppw v pp program current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp =v pp1, program in progress 822822822ma v pp = v pp2 (12v) program in progress i ppe v pp erase current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 ma v pp = v pp1, erase in progress 82216451645ma v pp = v pp2 (12v) , erase in progress i ppes / i ppws v cc erase suspend current 1,4 0.250.250.25a v pp = v pp1, program or erase suspend in progress 50 200 50 200 50 200 a v pp = v pp2 (12v) , program or erase suspend in progress notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a =+25 c. 2. the test conditions v cc max, v ccq max, v cc min, and v ccq min refer to the maximum or minimum v cc or v ccq voltage listed at the top of each column. v cc max = 3.3 v for 0.25 m 32-mbit devices. 3. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 4. sampled, not 100% tested. 5. i cces or i ccws is specified with the flash memory device deselected. ? if the device is read while in erase suspend, the current draw is the sum of i cces and i ccr . ? if the device is read while in program suspend, the current draw is the sum of i ccws and i ccr . table 13. dc current characteristics (sheet 2 of 2) sym parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note typ max typ max typ max
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 36 order number: 290580, revision: 020 7.2 dc voltage characteristics table 14. dc voltage characteristics symbol parameter v cc 2.7 v?3.6 v 2.7 v?2.85 v 2.7 v?3.3 v unit test conditions v ccq 2.7 v?3.6 v 1.65 v?2.5 v 1.8 v?2.5 v note min max min max min max v il input low voltage ?0.4 v cc * 0.22 v ?0.4 0.4 ?0.4 0.4 v v ih input high voltage 2.0 v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v ccq ? 0.4v v ccq +0.3v v v ol output low voltage ?0.1 0.1 -0.1 0.1 -0.1 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage v ccq ?0.1v v ccq ? 0.1v v ccq ? 0.1v v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock- out voltage 11.0 1.0 1.0v complete write protection v pp1 v pp during program / erase operations 1 1.65 3.6 1.65 3.6 1.65 3.6 v v pp2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 v v lko v cc prog/ erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/ erase lock voltage 1.2 1.2 1.2 v notes: 1. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 2. v pp = 11.4 v?12.6 v can be applied during program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp can be connected to 12 v for a total of 80 hours maximum.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 37 8.0 ac characteristics 8.1 ac read characteristics table 15. read operations?8-mbit density #symparameter density 8 mbit unit product 90 ns 110 ns v cc 3.0 v ? 3.6 v 2.7 v ? 3.6 v 3.0 v ? 3.6 v 2.7 v ? 3.6 v note min max min max min max min max r1 t avav read cycle time 3,4 80 90 100 110 ns r2 t avqv address to output delay 3,4 80 90 100 110 ns r3 t elqv ce# to output delay 1,3,4 80 90 100 110 ns r4 t glqv oe# to output delay 1,3,4 30 30 30 30 ns r5 t phqv rp# to output delay 3,4 150 150 150 150 ns r6 t elqx ce# to output in low z 2,3,4 0 0 0 0 ns r7 t glqx oe# to output in low z 2,3,4 0 0 0 0 ns r8 t ehqz ce# to output in high z 2,3,4 20 20 20 20 ns r9 t ghqz oe# to output in high z 2,3,4 20 20 20 20 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,4 0 0 0 0 ns notes: 1. oe# can be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 10 ?read operation waveform? on page 40 . 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 38 order number: 290580, revision: 020 table 16. read operations?16-mbit density #sym param eter density 16 mbit unit notes product 70 ns 80 ns 90 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.6 v 2.7 v?3.6 v 3.0 v? 3.6v 2.7 v?3.6v min max min max min max min max min max min max r1 t avav read cycle time 70 80 80 90 100 110 ns 3,4 r2 t avqv address to output delay 70 80 80 90 100 110 ns 3,4 r3 t elqv ce# to output delay 70 80 80 90 100 110 ns 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 ns 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 ns 3,4 r6 t elqx ce# to output in low z 0 0 0 0 0 0 ns 2,3,4 r7 t glqx oe# to output in low z 0 0 0 0 0 0 ns 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 ns 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 ns 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 0 0 0 0 0 0 ns 2,3,4 notes: 1. oe# can be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 10 ?read operation waveform? on page 40 . 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 39 table 17. read operations?32-mbit density #sym param eter density 32 mbit unit notes product 70 ns 90 ns 100 ns 110 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v 3.0 v?3.3 v 2.7 v?3.3 v 3.0 v?3.3 v 2.7 v?3.3 v min max min max min max min max min max min max r1 t avav read cycle time 70 90 90 100 100 110 ns 3,4 r2 t avqv address to output delay 70 90 90 100 100 110 ns 3,4 r3 t elqv ce# to output delay 70 90 90 100 100 110 ns 1,3,4 r4 t glqv oe# to output delay 20 20 30 30 30 30 ns 1,3,4 r5 t phqv rp# to output delay 150 150 150 150 150 150 ns 3,4 r6 t elqx ce# to output in low z 0 0 0 0 0 0 ns 2,3,4 r7 t glqx oe# to output in low z 0 0 0 0 0 0 ns 2,3,4 r8 t ehqz ce# to output in high z 20 20 20 20 20 20 ns 2,3,4 r9 t ghqz oe# to output in high z 20 20 20 20 20 20 ns 2,3,4 r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 0 0 0 0 0 0 ns 2,3,4 notes: 1. oe# can be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 10 ?read operation waveform? on page 40 . 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 40 order number: 290580, revision: 020 table 18. read operations ? 64-mbit density #sym parameter density 64 mbit unit product 70 ns 80 ns v cc 2.7 v?3.6 v 2.7 v?3.6 v note min max min max r1 t avav read cycle time 3,4 70 80 ns r2 t avqv address to output delay 3,4 70 80 ns r3 t elqv ce# to output delay 1,3,4 70 80 ns r4 t glqv oe# to output delay 1,3,4 20 20 ns r5 t phqv rp# to output delay 3,4 150 150 ns r6 t elqx ce# to output in low z 2,3,4 0 0 ns r7 t glqx oe# to output in low z 2,3,4 0 0 ns r8 t ehqz ce# to output in high z 2,3,4 20 20 ns r9 t ghqz oe# to output in high z 2,3,4 20 20 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 2,3,4 0 0 ns notes: 1. oe# can be delayed up to t elqv? t glqv after the falling edge of ce# without impact on t elqv . 2. sampled, but not 100% tested. 3. see figure 10 ?read operation waveform? on page 40 . 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. figure 10. read operation waveform r5 r10 r7 r6 r9 r4 r8 r3 r1 r2 r1 a ddress [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p]
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 41 8.2 ac write characteristics table 19. write operations?8-mbit density #sym parameter density 8 mbit unit product 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 90 110 note min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 4,5 50 60 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 50 50 60 60 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 50 60 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 2,4,5 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). so t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). so t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 27 ?bus operations (1) ? on page 51 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 5. see figure 11 ?write operations waveform? on page 45 .
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 42 order number: 290580, revision: 020 table 20. write operations?16-mbit density #symparameter density 16 mbit unit product 70 ns 80 ns 90 ns 110 ns v cc 3.0 v ? 3.6 v 80 100 2.7 v ? 3.6 v 70 80 90 110 note min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 0 0 0 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 45 50 50 60 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 40 50 50 60 60 ns w5 t av w h / t aveh address setup to we# (ce#) going high 2,4,5 50 50 50 60 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 0 0 0 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 0 0 0 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 0 0 0 0 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). so t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). so t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 27 ?bus operations (1) ? on page 51 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 5. see figure 11 ?write operations waveform? on page 45 .
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 43 table 21. write operations?32-mbit density #sym parameter density 32 mbit unit product 70 ns 90 ns 100 ns 110 ns v cc 3.0 v ? 3.6 v 6 90 100 2.7 v ? 3.6 v 70 90 100 110 note min min min min min min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 150 150 150 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5000000ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 45 60 60 70 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 40 50 60 60 60 ns w5 t av w h / t aveh address setup to we# (ce#) going high 2,4,5506060707070ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5000000ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5000000ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5000000ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 25 30 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 200 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 0 0 0 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4000000ns w13 t qvbl wp# hold from valid srd 3,4 0 0 0 0 0 0 ns w14 t whgl we# high to oe# going low 3,4 30 30 30 30 30 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). so t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). so t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 27 ?bus operations (1) ? on page 51 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 5. see figure 11 ?write operations waveform? on page 45 . 6. v cc max = 3.3 v for 32-mbit 0.25 micron product.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 44 order number: 290580, revision: 020 table 22. write operations?64-mbit density # symbol parameter density 64 mbit unit product 80 ns v cc 2.7 v ? 3.6 v note min w1 t phwl / t phel rp# high recovery to we# (ce#) going low 4,5 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 4,5 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 1,4,5 60 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2,4,5 40 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2,4,5 60 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 4,5 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2,4,5 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2,4,5 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 1,4,5 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3,4,5 200 ns w11 t qvvl v pp hold from valid srd 3,4 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3,4 0 ns w13 t qvbl wp# hold from valid srd 3,4 0 ns w14 t whgl we# high to oe# going low 3,4 30 ns notes: 1. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). so t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). so t wph =t whwl =t ehel =t whel =t ehwl . 2. refer to table 27 ?bus operations (1) ? on page 51 for valid a in or d in . 3. sampled, but not 100% tested. 4. see figure 12 ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 5. see figure 11 ?write operations waveform? on page 45 .
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 45 8.3 erase and program timing table 23. erase and program timing figure 11. write operations waveform symbol parameter v pp 1.65 v?3.6 v 11.4 v?12.6 v unit note typ max typ max t bwpb 4-kw parameter block word program time 1, 2, 3 0.10 0.30 0.03 0.12 s t bwmb 32-kw main block word program time 1, 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 word program time for 0.13 and 0.18 micron product 1, 2, 3 12 200 8 185 s word program time for 0.25 micron product 1, 2, 3 22 200 8 185 s t whqv2 / t ehqv2 4-kw parameter block erase time 1, 2, 3 0.5 4 0.4 4 s t whqv3 / t ehqv3 32-kw main block erase time 1, 2, 3 1 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 1,3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 1,3 5 20 5 20 s notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. w1 0 w1 w7 w4 w9 w9 w3 w3 w2 w6 w8 w5 a ddress [a] ce# [e] we# [w] oe# [g] data [d/q] rp# [p] vpp [v]
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 46 order number: 290580, revision: 020 8.4 ac i/o test conditions note: input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst-case speed conditions are when v cc = v cc min. note: see table 24 for component values. 8.5 device capacitance t a = 25 c, f = 1 mhz figure 12. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input outpu t figure 13. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 out table 24. test configuration component values for worst case speed conditions test configuration c l (pf) r 1 (k ? )r 2 (k ? ) v ccq min standard test 50 25 25 note: c l includes jig capacitance. table 25. device capacitance symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v sampled, not 100% tested.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 47 9.0 power and reset specifications 9.1 power-up/down characteristics to prevent any condition that might result in a spurious write or erase operation, power-up v cc and v ccq together. conversely, v cc and v ccq must power-down together. also power-up v pp with or slightly after v cc . conversely, v pp must power-down with or slightly before v cc . if v ccq and/or vpp are not connected to the v cc supply, then v cc must attain v cc min before applying vccq and vpp. device inputs must not be driven before supply voltage = vccmin. power supply transitions must occur only when rp# is low. 9.1.1 rp# connected to system reset use rp# during system reset with automated program/erase devices, because the system expects to read from the flash memory when the system exits reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization does not occur, because the flash memory might be providing status information instead of array data. connecting rp# to the system cpu reset# signal to allow proper cpu/flash initialization after a system reset. system designers must guard against spurious writes when v cc voltages are above v lko . because both we# and ce# must be low for a command write, driving either signal to v ih inhibits writes to the flash memory device. the cui architecture provides additional protection, because memory contents can be altered only after successful completion of the two-step command sequences. the flash memory device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 9.1.2 v cc , v pp, and rp# transitions the cui latches commands as issued by system software, and is not altered by v pp or ce# transitions or wsm actions. the cui default state upon power-up, after exit from reset mode or after v cc transitions above v lko (lockout voltage), is read-array mode. after any program or block-erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read-array mode, using the read array command if access to the flash-memory array is required.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 48 order number: 290580, revision: 020 9.2 reset specifications table 26. reset specifications symbol parameter v cc 2.7 v ? 3.6 v unit notes min max t plph rp# low to reset during read (if rp# is tied to v cc , this specification is not applicable) 100 ns 1, 2 t plrh1 rp# low to reset during block erase 22 s 3 t plrh2 rp# low to reset during program 12 s 3 notes: 1. if t plph is < 100 ns, the device can still reset, but reset is not guaranteed. 2. if rp# is asserted while a block erase or word program operation is not executing, the reset completes within 100 ns. 3. sampled, but not 100% tested. figure 14. deep power-down/reset operations waveforms ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plr h t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 49 9.3 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers must consider the following three supply current issues: 1. standby current levels (i ccs ). 2. read current levels (i ccr ). 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device output capacitive and inductive loading. two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. each flash device must have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high-frequency, inherently low-inductance capacitors must be placed as close as possible to the package leads. 9.4 power consumption intel ? flash memory devices use a tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the flash memory device is selected but idle. if ce# is deasserted, the flash memory device enters its standby mode, where current consumption is even lower. the combination of these features can minimize memory power consumption, and therefore minimize overall system power consumption. 9.4.1 active power when ce# is at a logic - low level and rp# is at a logic - high level, the flash memory device is in the active mode. refer to the dc characteristic tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current can profoundly affect system power consumption, especially for battery - operated devices. 9.4.2 automatic power savings (aps) automatic power savings provides low - power operation during read mode. after data is read from the flash memory array and the address lines are quiescent, aps circuitry places the flash memory device in a mode where typical current is comparable to i ccs . the flash memory stays in this static state with outputs valid until a new location is read. 9.4.3 standby power when ce# is at a logic - high level (v ih ) and the flash memory device is in read mode, the flash memory is in standby mode. this mode disables much of the device circuitry, and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the status of the oe# signal. if ce# transitions to a logic - high level during erase or program operations, the flash memory device continues to perform the operation and consume corresponding active power until the operation is completed. system engineers must analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this approach provides a more accurate measure of application - specific power and energy requirements.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 50 order number: 290580, revision: 020 9.4.4 deep power-down mode the deep power-down mode is activated when rp# = v il (gnd 0.2 v). during read modes, rp# going low deselects the flash memory and places the outputs in a high-impedance state. recovery from deep power-down mode requires a minimum time of t phqv (see ?ac read characteristics? on page 37 ). during program or erase modes, rp# transitioning low aborts the in-progress operation. the memory contents of the address being programmed or the block being erased are no longer valid, because the abort compromises data integrity. during deep power-down, all internal circuits switch to a low-power savings mode (rp# transitioning to v il or turning off power to the flash memory device clears the status register). 10.0 operations overview flash memory combines eeprom functionality with in-circuit electrical program-and-erase capability. the b3 flash memory device family uses a command user interface (cui) and automated algorithms to simplify program and erase operations. the cui allows for 100% cmos-level control inputs and fixed power supplies during erasure and programming. when v pp < v pplk , the flash memory device executes only the following commands successfully: read array read status register clear status register read identifier the flash memory device provides standard eeprom read, standby, and output-disable operations. manufacturer identification and device identification data can be accessed through the cui. all functions that alter memory contents (program and erase) are accessible through the cui. the internal write state machine (wsm) completely automates program and erase operations, while the cui signals the start of an operation and the status register reports status. the cui handles the we# interface to the data and address latches, and system status requests during wsm operation.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 51 10.1 bus operations the b3 flash memory device performs read, program, and erase in-system operations through the local cpu or microcontroller. all bus cycles to or from the flash memory conform to standard microcontroller bus cycles. four control pins dictate the data flow in and out of the flash memory device: ce# oe# we# rp# table 27 summarizes these bus operations. 10.1.1 read the b3 flash memory device provides four read modes: read array read identifier read status read query these modes are accessible independently of the v pp voltage. issue the appropriate read mode command to the cui to enter the corresponding mode. upon initial device power - up or after exit from reset, the flash memory device automatically defaults to read-array mode. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control. when active, ce# enables the flash memory device. oe# is the data output control, and drives the selected memory data onto the i/o bus. for all read modes, we# and rp# must be at v ih . figure 10 on page 40 illustrates a read cycle. table 27. bus operations (1) mode note rp# ce# oe# we# dq 0?7 dq 8?15 read (array, status, or identifier) 2?4 v ih v il v il v ih d out d out output disable 2 v ih v il v ih v ih high z high z standby 2 v ih v ih x x high z high z reset 2, 7 v il x x x high z high z write 2, 5?7 v ih v il v ih v il d in d in notes: 1. 8-bit devices use only dq[0:7]. 16-bit devices use dq[0:15]. 2. x must be v il , v ih for control pins and addresses. 3. see dc characteristics for v pplk , v pp1 , v pp2 , v pp3 , v pp4 voltages. 4. manufacturer and device codes can also be accessed in read identifier mode (a 1 ?a 21 =0). see table 29 . 5. refer to table 30 for valid d in during a write operation. 6. to program or erase the lockable blocks, hold wp# at v ih . 7. rp# must be at gnd 0.2 v to meet the maximum deep power-down current specified.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 52 order number: 290580, revision: 020 10.1.2 output disable when oe# is at a logic - high level (v ih ), the flash memory device outputs are disabled. output pins are placed in a high - impedance state. 10.1.3 standby deselecting the flash memory device by bringing ce# to a logic - high level (v ih ) places the device in standby mode. standby mode substantially reduces device power consumption, without any latency for subsequent read accesses. in standby mode, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the flash memory device continues to consume active power until the program or erase operation is complete. 10.1.4 deep power-down / reset from read mode, rp# at v il for time t plph does the following: deselects the flash memory. places output drivers in a high - impedance state. turns off all internal circuits. after a return from reset, a time t phqv is required until the initial read-access outputs are valid. after a return from reset, a delay (t phwl or t phel ) is required before a write can be initiated. after this wake - up interval, normal operation is restored. the cui resets to read-array mode, and the status register is set to 80h. figure 14 ?deep power-down/reset operations waveforms? on page 48 (a) illustrates this case. if rp# is taken low for time t plph during a program or erase operation, the operation aborts. the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data might be partially erased or written. the abort process uses the following sequence: 1. when rp# goes low, the flash memory device shuts down the operation in progress, a process that takes time t plrh to complete. 2. after this time t plrh , the flash memory device either resets to read-array mode (if rp# has gone high during t plrh , see figure 14 ?deep power-down/reset operations waveforms? on page 48 (b) ), or enters reset mode (if rp# is still logic low after t plrh , see figure 14 ?deep power-down/reset operations waveforms? on page 48 ( c) ). 3. in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl / t phel must elapse before initiating a read or write operation, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rp# goes high. as with any automated device, rp# must be asserted during system reset. when the system finishes reset, the processor expects to read from the flash memory. automated flash memories provide status information when read during program or block-erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization cannot occur, because the flash memory might be providing status information instead of array data. intel ? flash memories allow proper cpu initialization after a system reset, using the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 53 10.1.5 write a write occurs when both ce# and we# are low and oe# is high. commands are written to the command user interface (cui) using standard microprocessor write timings to control flash memory operations. the cui does not occupy an addressable memory location. the address and data buses are latched on the rising edge of the second we# or ce# pulse, whichever occurs first. table 30 shows the available commands, and appendix a provides detailed information about moving between the different modes of operation using cui commands. two commands modify array data: program (40h). erase (20h). writing either of these commands to the internal command user interface (cui) initiates a sequence of internally timed functions that culminate in the completion of the requested task (unless that operation is aborted by either rp# being driven to v il for t plrh or an appropriate suspend command). 11.0 operating modes the flash memory device has four read modes: read array read identifier read status read query see figure 1 ?b3 architecture block diagram? on page 10 ). the flash memory device also has two write modes: program block erase three additional modes are available only during suspended operations: erase suspend to program erase suspend to read program suspend to read table 28 ?command codes and descriptions? on page 54 summarizes the commands used to reach these modes. appendix a, ?write state machine current/next states,? is a comprehensive chart showing the state transitions.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 54 order number: 290580, revision: 020 11.1 read array when rp# transitions from v il (reset) to v ih , the flash memory device defaults to read-array mode and responds to the read-control inputs (ce#, address inputs, and oe#) without any additional cui commands. when the flash memory device is in read-array mode, four control signals control data output: we# must be logic high (v ih ) ce# must be logic low (v il ) oe# must be logic low (v il ) rp# must be logic high (v ih ) in addition, the address of the preferred location must be applied to the address pins. if the flash memory device is not in read-array mode, such as after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can occur. table 28. command codes and descriptions (sheet 1 of 2) code device mode description 00, 01, 60, 2f, c0, 98 invalid/ reserved unassigned commands that must not be used. intel reserves the right to redefine these codes for future functions. ff read array places the flash memory device in read-array mode, so that array data is output on the data pins. 40 program set-up a two-cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information, and initiates the wsm to execute the program algorithm. the flash memory device outputs status register data when ce# or oe# is toggled. to read array data, a read array command is required after programming. see section 11.4 . 10 alternate program set-up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui does the following: 1. sets both sr.4 and sr.5 of the status register to 1. 2. places the flash memory device into the read-status register mode. 3. waits for another command. see section 11.5, ?erase mode? on page 58 . d0 erase confirm program / erase resume if the previous command was an erase set-up command, then the cui closes the address and data latches, and begins erasing the block indicated on the address pins. during erase, the flash memory device responds only to the read status register and erase suspend commands. the device outputs status register data when ce# or oe# is toggled. if a program or erase operation was previously suspended, this command resumes that operation.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 55 note: see chapter 14.0, ?write state machine current/next states,? for mode transition information. b0 program / erase suspend issuing this command suspends the currently executing program/erase operation. to indicate when the operation has been successfully suspended, the status register sets either the program suspend (sr.2) or erase suspend (sr.6), and sets the wsm status bit (sr.7) to 1 (ready). the wsm continues to idle in the suspend state, regardless of the state of all input-control pins except rp#, which immediately shuts down the wsm and the remainder of the device, if it is driven to v il . see section 11.4.1, ?suspending and resuming programming? on page 58 and section 11.4.1, ?suspending and resuming programming? on page 58 . 70 read status register this command places the flash memory device into read-status register mode. reading the device outputs the contents of the status register, regardless of the address presented to the device. the flash memory device automatically enters this mode after a program or erase operation is initiated. see section 11.3, ?read status register? on page 56 . 50 clear status register the wsm can set the block-lock status (sr.1), v pp status (sr.3), program status (sr.4), and erase status (sr.5) bits in the status register to 1. however, the wsm cannot clear these bits to 0. issuing this command clears these bits to 0. 90 read identifier places the flash memory device into the intelligent-identifier-read mode, so that reading the device outputs the manufacturer and device codes (a 0 = 0 for manufacturer, a 0 = 1 for the device; all other address inputs must be 0). see section 11.2, ?read identifier? on page 56 . table 28. command codes and descriptions (sheet 2 of 2) code device mode description
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 56 order number: 290580, revision: 020 11.2 read identifier to read the manufacturer and device codes, the flash memory device must be in read-identifier mode, which can be reached by writing the read identifier command (90h). as shown in table 29 , once in read-identifier mode: a 0 = 0 outputs the manufacturer identification code. a 0 = 1 outputs the device identifier. note: a 1 ?a 21 = 0. to return to read-array mode, write the read-array command (ffh). 11.3 read status register the flash memory device status register indicates when a program or erase operation is complete, and the success or failure of that operation. to read the status register, issue the read status register (70h) command to the cui. this command causes all subsequent read operations to output data from the status register until another command is written to the cui. to return to reading from the array, issue the read array (ffh) command. the status register bits are output on dq 0 ?dq 7 . the upper byte, dq 8 ?dq 15 , outputs 00h during a read status register command. the contents of the status register are latched on the falling edge of oe# or ce#, which prevents possible bus errors that might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register does not indicate completion of a program or erase operation. when the wsm is active, sr.7 indicates the status of the wsm. the remaining bits in the status register indicate whether the wsm was successful in performing the preferred operation (see table 31 on page 60 ). table 29. read identifier table size mfr. id device identifier -t (top boot) -b (bottom boot) 28f004b3 0089h d4h d5h 28f400b3 8894h 8895h 28f008b3 0089h d2h d3h 28f800b3 8892h 8893h 28f016b3 d0h d1h 28f160b3 0089h 8890h 8891h 28f320b3 8896h 8897h 28f640b3 8898h 8899h
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 57 11.3.1 clearing the status register the wsm sets status bits 1 through 7 to 1, and clears bits 2, 6, and 7 to 0. however, the wsm cannot clear status bits 1 or 3 through 5 to 0. because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations can be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note: the read array command must be issued before data can be read from the flash memory array. 11.4 program mode programming is executed using a two - write sequence. 1. the program setup command (40h) is written to the cui. 2. a second write specifies the address and data to program. the wsm executes a sequence of internally timed events to program preferred bits of the addressed location. the wsm then verifies that the bits are sufficiently programmed. programming the memory changes specific bits within an address location to 0. if users attempt to program 1 instead of 0, the memory cell contents do not change and no error occurs. the status register indicates the programming status: while the program sequence executes, status bit 7 is 0. to poll the status register, toggle either ce# or oe#. while programming, the only valid commands are: read status register program suspend program resume when programming is complete, the program-status bits must be checked. if the programming operation was unsuccessful, sr.4 is set, indicating a program failure. if sr.3 is set, then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted on a locked block and the operation aborted. clear the status register before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read-array mode.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 58 order number: 290580, revision: 020 11.4.1 suspending and resuming programming the program suspend command halts the in-progress program operation to read data from another flash memory location. 1. after the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). 2. the flash memory device continues to output status register data after the program suspend command is written. 3. polling sr.7 and sr.2 determines when the program operation has been suspended (both are set to 1). t whrh1 /t ehrh1 specifies the program- suspend latency. 4. a read array command can now be written to the cui to read data from blocks other than the suspended block. the only other valid commands while program is suspended are: ? read status register ? read identifier ?program resume 5. after the program resume command is written to the flash memory, the wsm continues with the program process, and status register bits sr.2 and sr.7 are automatically cleared. 6. after the program resume command is written, the flash memory device automatically outputs status register data when read. see appendix b, ?program and erase flowcharts.? note: v pp must remain at the same v pp level used for program while in program-suspend mode. rp# must also remain at v ih. 11.5 erase mode to erase a block: 1. write the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure sets all bits within the block to 1. only one block can be erased at a time. 2. the wsm executes a sequence of internally timed events : a. programs all bits within the block to 0. b. erases all bits within the block to 1. c. verifies that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is 0.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 59 3. when the status register indicates that erasure is complete, check the erase-status bit to verify that the erase operation was successful. ? if the erase operation was unsuccessful, sr.5 of the status register is set to 1, indicating an erase failure. ? if v pp was not within acceptable limits after the erase confirm command was issued, the wsm does not execute the erase sequence. instead, sr.5 is set to indicate an erase error, and sr.3 is set to 1, indicating that the v pp supply voltage was not within acceptable limits. 4. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed. 5. to prevent inadvertent status- register reads, place the flash memory device in read-array mode after the erase is complete. 11.5.1 suspending and resuming erase because an erase operation requires on the order of seconds to complete, an erase suspend command is provided. erase suspend interrupts an erase sequence to read data from?or program data to? another block in memory. after the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pauses the erase sequence at a predetermined point in the erase algorithm. note: the status register will indicates if/when the erase operation has been suspended. a read array/program command can now be written to the cui, to read data from/ program data to blocks other than the one currently suspended. the program command can subsequently be suspended to read yet another array location. the only valid commands while erase is suspended are: erase resume program read array read status register read identifier during erase-suspend mode, to place the flash memory device in a pseudo-standby mode, set ce# to v ih , which reduces active current consumption. erase resume continues the erase sequence when ce# = v il . as with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 60 order number: 290580, revision: 020 notes: pa: program address pd: program data ba: block address ia: identifier address id: identifier data srd: status register data 1. bus operations are defined in table 27 . 2. following the intelligent identifier command, two read operations access manufacturer and device codes. ? a 0 = 0 for manufacturer code. ? a 0 = 1 for device code. ? a 1 ?a 21 = 0. 3. either the 40h or 10h command is valid. the standard is 40h. 4. when writing commands to the flash memory device, the upper data bus [dq 8 ?dq 15 ] must be either v il or v ih , to minimize current draw. table 30. command bus definitions (1,4) first bus cycle second bus cycle command notes oper addr data oper addr data read array write x ffh read identifier 2 write x 90h read ia id read status register write x 70h read x srd clear status register write x 50h program 3 write x 40h / 10h write pa pd block erase/confirm write x 20h write ba d0h program/erase suspend write x b0h program/erase resume write x d0h table 31. status register bit definition wsms ess es ps vpps pss bls r 76543210 bits notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy check write state machine bit first to determine word program or block-erase completion, before checking program or erase- status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set at 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to 1, wsm has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in word program 0 = successful word program when this bit is set to 1, wsm has attempted but failed to program a word.
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 61 sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not continuously indicate the v pp level. the wsm interrogates the v pp level only after the program or erase command sequences are entered, and informs the system if v pp has not been switched on. the v pp is also checked before the wsm verifies the operation. the v pp status bit is not guaranteed to report accurate feedback between v pplk max and v pp1 min or between v pp1 max and v pp4 min. sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to 1. the pss bit remains set to 1 until a program resume command is issued. sr.1 = block lock status 1 = program/erase attempted on locked block; operation aborted 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, the wsm sets this bit. the operation specified is aborted and the flash memory device returns to read status mode. sr.0 = reserved for future enhancements (r) this bit is reserved for future use and must be masked out when polling the status register. note: a command sequence error is indicated when sr.4, sr.5, and sr.7 are set. bits notes:
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 62 order number: 290580, revision: 020 12.0 block locking the b3 flash memory device architecture features two hardware-lockable parameter blocks. 12.1 wp# = v il for block locking the lockable blocks are locked when wp# = v il ; any program or erase operation to a locked block results in an error, which is reflected in the status register: for top configuration, the top two parameter blocks are lockable: ? blocks #133 and #134 for 64 mbit ? blocks #69 and #70 for 32 mbit ? blocks #37 and #38 for 16 mbit ? blocks #21 and #22 for 8 mbit ? blocks #13 and #14 for 4 mbit for the bottom configuration, the bottom two parameter blocks are lockable. these are blocks #0 and #1 for 4, 8 , 16, 32, and 64 mbit. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 12.2 wp# = v ih for block unlocking wp# = v ih unlocks all lockable blocks. these blocks can now be programmed or erased. note: rp# does not override wp# locking for the b3 flash memory device, as in previous boot block devices. wp# controls all block locking. v pp provides protection against spurious writes. table 32 defines the write- protection methods. table 32. write-protection truth table for the b3 device family v pp wp# rp# write protection provided xxv il all blocks locked v il xv ih all blocks locked v pplk v il v ih lockable blocks locked v pplk v ih v ih all blocks unlocked
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 63 13.0 v pp program and erase voltages theb3 flash memory device products provide in-system programming and erase at 2.7 v. for customers requiring fast programming in their manufacturing environment, the b3 flash memory device includes an additional low-cost 12-v programming feature. the 12-v v pp mode enhances programming performance during the short period of time typically found in manufacturing processes. however, this mode is not intended for extended use. 12 v can be applied to v pp during program and erase operations for a maximum of 1000 cycles on the main blocks, and 2500 cycles on the parameter blocks. v pp can be connected to 12 v for a total of 80 hours maximum. warning: stressing the flash memory device beyond these limits might cause permanent damage. during read operations or idle times, v pp can be tied to a 5-v supply. for program and erase operations, a 5-v supply is not permitted. the v pp must be supplied with either 2.7 v to 3.6 v or 11.4 v to 12.6 v during program and erase operations. 13.1 v pp = v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash memory device. when v pp is below v pplk , any program or erase operation results in an error, prompting the corresponding sr.3 to be set. 14.0 additional information order number document/tool 297948 intel ? advanced boot block flash memory family specification update 292199 ap-641 achieving low power with the 3 volt advanced boot block flash memory 292200 ap-642 designing for upgrade to the 3 volt advanced boot block flash memory note 2 3 volt advanced boot block algorithms (?c? and assembly) http://developer.intel.com/design/flash/swtools contact your intel representative intel ? flash data integrator (ifdi) software developer?s kit 297874 ifdi interactive: play with intel ? flash data integrator on your pc notes: 1. call the intel literature center at (800) 548-4725 to request intel documentation. international customers must contact their local intel or distribution sales office. 2. visit the intel home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools. 3. for the most current information about intel ? advanced boot block flash memory and intel ? advanced+ boot block flash memory, visit http://developer.intel.com/design/flash/
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 64 order number: 290580, revision: 020 appendix a write state machine current/next states table 33. write state machine (sheet 1 of 2) command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read identifier. (90h) read array ?1? array read array program setup erase setup read array read status read array read identifier read status ?1? status read array program setup erase setup read array read status read array read identifier read identifier ?1? identifier read array program setup erase setup read array read status read array read identifier prog. setup ?1? status program (command input = data to be programmed) program (continue) ?0? status program (continue) prog. sysop. to rd. status program (continue) program suspend to read status ?1? status prog. susp. to read array program suspend to read array program (continue ) program susp. to read array program (continue ) prog. susp. to read status prog. susp. to read array prog. susp. to read identifier program suspend to read array ?1? array prog. susp. to read array program suspend to read array program (continue ) program susp. to read array program (continue ) prog. susp. to read status prog. sus. to read array prog. susp. to read identifier prog. susp. to read identifier ?1? identifier prog. susp. to read array program suspend to read array program (continue ) program susp. to read array program (continue ) prog. susp. to read status prog. sus. to read array prog. susp. to read identifier program (complete) ?1? status read array program setup erase setup read array read status read array read identifier erase setup ?1? status erase command error erase (continue ) erase cant. error erase (continue ) erase command error erase cant. error ?1? status read array program setup erase setup read array read status read array read identifier erase (continue) ?0? status erase (continue) erase sus. to read status erase (continue)
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 65 erase suspend to status ?1? status erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase susp. to read array ?1? array erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase susp. to read identifier ?1? identifier erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase (complete) ?1? status read array program setup erase setup read array read status read array read identifier table 33. write state machine (sheet 2 of 2) command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read identifier. (90h)
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 66 order number: 290580, revision: 020 appendix b program and erase flowcharts figure 15. program flowchart start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 comman d program setup program commen ts data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy comman d commen ts check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 67 figure 16. program suspend/resume flowchart start write b0h read status register no comments data = 70h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation write write read read standby standby write command read status read array program resume write 70h 0 data = b0h addr = x write program suspend
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 68 order number: 290580, revision: 020 figure 17. block erase flowchart start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby comman d erase setup erase confirm commen ts data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy comman d commen ts check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 69 figure 18. erase suspend/resume flowchart start write b0h read status register bus operation write write no command erase suspend read array comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 0 read read array data from block other than the one being erased. read status register data toggle ce# or oe# to update status register data addr = x standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.6 1 = erase suspended 0 = erase completed write erase resume data = d0h addr = x write read status data = 70h addr = x write 70h
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 18 aug 2005 intel ? advanced boot block flash memory (b3) datasheet 70 order number: 290580, revision: 020 appendix c ordering information figure 19. ordering information table 34. ordering information: valid combinations (sheet 1 of 2) 40-lead tsop 48-lead tsop 48-ball bga csp (1,2) 48-ball vf bga ext. temp. 64 mbit te28f640b3tc80 te28f640b3bc80 ge28f640b3tc80 ge28f640b3bc80 ext. temp. 32 mbit te28f320b3td70 te28f320b3bd70 te28f320b3tc70 te28f320b3bc70 te28f320b3tc90 te28f320b3bc90 te28f320b3ta100 te28f320b3ba100 te28f320b3ta110 te28f320b3ba110 js28f320b3td70 js28f320b3bd70 GE28F320B3TD70 ge28f320b3bd70 ge28f320b3tc70 ge28f320b3bc70 ge28f320b3tc90 ge28f320b3bc90 ph28f320b3bd70 package te = 48- lead tsop gt = 48-ball bga * csp ge = vf bga csp rc = eas y bga pc = pb free easy bga ph = pb free vfbga js = pb free tsop product line designator for all intel ? flash products access speed (ns ) (70, 80 , 90, 100 , 110 ) pr oduct fami l y c3 = 3 volt advanced boo t b v cc =2.7v?3.6v v pp =2.7v?3.6v or 11 .4 v?12.6 v devi ce densi ty 640=x16(64mbit) 320=x16(32mbit) 160=x16(16mbit) 800=x16(8mbit) t= top blocking b= bottom blocking lithography a = 0.25 m c = 0.18 m d = 0.13 m t e 2 8 f 3 2 0 b 3 t c 7 0
28f008/800b3, 28f016/160b3, 28f320b3, 28f640b3 datasheet intel ? advanced boot block flash memory (b3) 18 aug 2005 order number: 290580, revision: 020 71 ext. temp. 16 mbit te28f016b3ta90 te28f016b3ba90 te28f016b3ta110 te28f016b3ba110 te28f160b3td70 te28f160b3bd70 te28f160b3tc70 te28f160b3bc70 te28f160b3tc80 te28f160b3bc80 te28f160b3tc90 te28f160b3bc90 te28f160b3ta90 te28f160b3ba90 te28f160b3ta110 te28f160b3ba110 js28f160b3ta70 js28f160b3bd70 gt28f160b3ta90 (3) gt28f160b3ba90 (3) gt28f160b3ta110 (3) gt28f160b3ba110 (3) ge28f160b3td70 ge28f160b3bd70 ge28f160b3tc70 ge28f160b3bc70 ge28f160b3tc80 ge28f160b3bc80 ge28f160b3tc90 ge28f160b3bc90 ph28f160b3td70 ph28f160b3bd70 ext. temp. 8 mbit te28f800b3ta90 te28f800b3ba90 te28f800b3ta110 te28f800b3ba110 ge28f800b3ta70 ge28f800b3ba70 ge28f800b3ta90 ge28f800b3ba90 notes: 1. the 48-ball bga package top side mark reads f160b3. this mark is identical for both x8 and x16 products. all product shipping boxes or trays provide the correct information regarding bus architecture. however, once the flash memory devices are removed from the shipping media, differentiating based on the top side mark might be difficult. the device identifier (accessible through the device id command: see section 11.2, ?read identifier? on page 56 for further details) enables x8 and x16 bga package product differentiation. 2. the second line of the 48-ball bga package top side mark specifies assembly codes. for samples only, the first character signifies either: ? e for engineering samples, or ? s for silicon daisy-chain samples. all other assembly codes without an e or an s as the first character are production units. 3. intel recommends using.18 m intel ? advanced boot block products. ta ble 3 4. ordering information: valid combinations (sheet 2 of 2) 40-lead tsop 48-lead tsop 48-ball bga csp (1,2) 48-ball vf bga

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